The present application claims the benefit of Korean Patent Application No. 87293/2000 filed Dec. 30, 2000, which is herein fully incorporated by reference.
1. Field of the Invention
The present invention relates to a circuit and method for programming and reading a multi-level flash memory, which provide sufficient intervals between threshold voltage distributions and improve the level sensing speed of the flash memory.
2. Discussion of the Related Art
A non-volatile memory maintains its stored data even when its power source disappears. EPPROM or EEPROM is a non-volatile memory that does not require a refresh operation, as compared to SRAMs. EEPROM that erases data stored in its memory cells by block units, instead of byte units, is known as a flash memory.
A conventional flash memory includes a plurality of memory cells for storing data. Each memory cell generally includes a transistor having a floating gate. To store data in the memory cells of a flash memory, i.e., to program the flash memory, certain amounts of electrons are injected into the floating gates of the memory cells to set the threshold levels of the memory cells to desired levels. Different threshold levels set in the memory cells represent different data. Generally, the threshold levels of the memory cells are detected and compared with predetermined reference levels provided by reference cells, so as to determine the different levels of the memory cells. For instance, in a memory cell having two levels (i.e., it stores one-bit information), If the memory cell has a first threshold level, it may represent a storage of xe2x80x9c0xe2x80x9d for the one bit, whereas if the memory cell has a second threshold level, it may represent a storage of xe2x80x9c1xe2x80x9d for the bit. In this manner, each memory cell of the flash memory can store multiple levels corresponding to multiple bit information.
To erase the flash memory, the electrons injected in the floating gates are extracted from the floating gates to reduce the threshold voltages of the cell transistors to desired levels.
There exist different conventional methods for programming and reading a flash memory. For example, the EEPROM flash memory can be programmed by repeating short durations of programming and verifying operations until the desired threshold levels have been set for the memory cells. In another example, the flash memory can be programmed by applying a long program pulse to the memory cells until the memory cells are programmed with the desired threshold levels and then releasing all programming conditions once the memory cells are programmed.
A method of reading a multi-level flash memory according to a related art, involves applying one fixed voltage to the control gates of memory cells and reference cells and simultaneously comparing the threshold voltage of the memory cells with different reference voltages using a sensing amplifier. Here, the sensing amplifier includes an X number of comparators wherein X=[(the number of levels)xe2x88x921]. The comparators are used to determine the levels of the memory cells.
FIG. 1A is a diagram of a related art circuit in which the above-described method of reading the flash memory can be implemented. As shown, this circuit is constructed with a memory cell 10 for storing two-bit data (four levels), a drain bias unit 12 for supplying a drain of the memory cell 10 with a power source voltage Vdd, a reference cell block 14 for producing three kinds of reference currents ref1, ref2, and ref3, three comparators 16, 18, and 20 for comparing respectively the reference currents ref1, ref2, and ref3 to the drain current of the memory cell 10, and a decoding unit 22 for outputting 2-bit data made of MSB (most significant bit) and LSB (least significant bit) by decoding outputs X1, X2, and X3 of the comparators 16, 18, and 20 according to known techniques.
In the circuit of FIG. 1A, a fixed voltage is applied to the control gates of the memory cell 10 and reference cells in the reference cell block 14. As a result, a drain current or cell current xe2x80x9cIcellxe2x80x9d of the memory cell 10 is applied to the comparators 16, 18 and 20, and at the same time, the reference currents ref1, ref2, and ref3 having different ranges are applied simultaneously to the comparators 16, 18, and 20, respectively. The comparators 16, 18, and 20 compare the cell current Icell with the corresponding reference current to output comparison results X1, X2 and X3. The decoding unit 22 outputs MSB and LSB (2 bit/four levels) in accordance with the comparison results X1, X2, and X3. For example, if the comparison results indicate that the cell current Icell of the memory cell 10 is at a level 4, then the decoding unit 22 may output (1, 1) as MSB and LSB.
FIG. 1B is a graph showing threshold voltage distributions of the circuit of FIG. 1A according to a related art. As shown in FIG. 1B, the memory cell 10 can store two-bits (MSB and LSB) of information. That is, the memory cell 10 has four possible levels (0,0), (0,1), (1,0) and (1,1), which are detected by using the reference currents ref1, ref2 and ref3. The reference currents ref1, ref2, and ref3 are distributed in accordance with a distribution size of a threshold voltage Vt of the memory cell 10, so as to fall between two of the possible threshold voltage distributions of the circuit.
Despite the advantage that a particular level of a multi-level memory cell can be sensed by a single operation using the multiple comparators 16, 18 and 20, the circuit of FIG. 1A suffers from the following problems. In the circuit of FIG. 1A, a large number of voltage distributions must be made within a limited voltage range or threshold voltage window. For example, as shown in FIGS. 1B and 1C, a four-level (2 bit) flash memory requires four different threshold voltage distributions for the memory cell, and three different reference currents/voltages therebetween, a total of seven voltage distributions within an allotted threshold voltage window. In another example, a 4-bit flash memory requires 16 threshold voltage distributions for the memory cells and 15 reference current cells/voltages, a total of thirty-one (31) voltage distributions within an allotted threshold voltage window. This crowds the voltage threshold window and causes errors in level detections. Particularly, as the number of bits representing the respective levels of the flash memory increases, this decreases significantly a margin for establishing the threshold voltage distributions within the threshold voltage window, rendering the problem much more serious for high-bit flash memories. In this regard, it becomes extremely difficult and ineffective to use the above-described conventional method to read a memory cell stored with over 3 bits of information.
FIG. 2A is a diagram of a circuit for programming and reading a multi-level flash memory according to another related art and FIG. 2B shows an example of a graph of threshold voltage distributions for the circuit of FIG. 2A. As shown, this circuit is constructed with a memory cell 30 for storing data, a drain bias unit 32 for supplying a drain of the memory cell 30 with a power source voltage Vdd, a reference cell block 34 for producing a reference voltage Vref, a single comparator 36 for comparing the reference voltage Vref to a drain voltage of the memory cell 30, and a decoding unit 38 for outputting two bits MSB and LSB of data by decoding an output X4 of the comparator 36.
In the circuit of FIG. 2A, a voltage Vgs is applied to the control gates of the memory cell 30 and a reference cell of the reference cell block 34, wherein the voltage Vgs is increased (or decreased) sequentially by three steps to voltage V1, V2, and then V3, as shown in FIG. 2C. As a result, the reference voltage Vref of varying range is applied one at a time to the comparator 36 depending on the voltage Vgs, and a drain voltage Vcell of the memory cell 30 corresponding to the drain current Icell of the memory cell 30 is also applied to the comparator 36. The comparator 36 compares the drain voltage Vell with the reference voltage Vref, and the decoding unit 38 outputs MSB and LSB in accordance with an output of the comparator 36.
Although the circuit of FIG. 2A may allow multi-level sensing using only one sense amplifier and one reference cell, the sensing speed of this circuit is slow and the circuit may require additional components to complete its operation. For example, sensing different levels of 2-bit memory cell, 3-bit memory cell, and 4-bit memory requires that a control voltage Vgs applied to the memory cell be stepped through at least 3, 7 and 15 different voltages, respectively. Thus, the circuit and method of FIG. 2A require at least [(number of level)xe2x88x921] voltage variance steps, wherein a total number of voltage variance steps required for the memory cell increases 2n times as the number of bits allotted to the memory cell. This causes a serious problem of slowing down the level sensing speed of the circuit.
The above-described and other conventional techniques for programming and reading a flash memory are disclosed in U.S. Pat. No. 5,172,338 and U.S. Pat. No. 5,717,632, each of which is herein fully incorporated by reference.
Therefore, a need exists for an improved circuit and method for programming and reading a multi-level flash memory, which overcome problems associated with conventional circuits and methods.
Accordingly, the present invention is directed to a circuit and method for programming and reading a multi-level flash memory that substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit and method for programming and reading a multi-level flash memory that provide sufficient intervals between threshold voltage distributions and improve the level sensing speed of the memory.
Another object of the present invention is to provide a circuit and method for programming and reading a multi-level flash memory, i.e. having a plurality of levels represented by k bit(s) (k=n+m) where n and m are respectively upper and lower numbers of bits, by programming and distributing threshold voltages of memory and reference current cells, constructing n upper bits using a sense amplifier having [(level number)xe2x88x921] comparison circuits to distinguish the respective levels and a constant control gate voltage, and constructing m lower bits by varying a control gate voltage with a sense amplifier having one comparison circuit enabling to judge two levels represented by 1 bit.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, in a flash memory including a plurality of flash memory cells having 2n+m levels represented by upper n bits and lower m bits, a circuit for programming and reading the flash memory according to an embodiment of the present invention, comprises an upper bit reference cell block for supplying reference cell currents for constructing n upper bits in total (n+m) bits for representing multi-levels of the memory cell, a lower bit reference cell block for supplying reference currents for constructing m lower bits in the total (n+m) bits for representing multi-levels of the memory cell, a cell gate voltage supplying unit for supplying each control gate of the memory cells with a voltage, a memory cell program/read unit for reading or programming levels of the memory cell by comparing a drain voltage of the memory cell to the reference current, and a data register for storing an output data of the memory cell program/read unit or supplying the memory cell program/read unit with the stored data.
In another aspect of the present invention, in a flash memory including a plurality of flash memory cells having 2n+m levels represented by upper n bits and lower m bits, a method of programming and reading a flash memory with multiple levels, includes the steps of programming reference currents so as to supply (2nxe2x88x921) reference current cells with threshold voltages having a predetermined interval each other wherein the reference current cells are taken as references for distinguishing the upper n bits, programming reference currents so as to supply 2n reference current cells with threshold voltages having a predetermined interval each other when the reference current cells are taken as references for distinguishing the lower m bits, programming a threshold voltage of the memory cell so as to be allocated to one of the 2n+m threshold voltages, sensing the upper n bits through one step and storing the upper n bits in a data register using (2nxe2x88x921) comparison circuits for comparing currents from the (2nxe2x88x921) upper bit reference current cells to a drain current of the memory cell, and sensing the upper n bits by varying a voltage applied to a control gate of the memory cell through (2mxe2x88x921) steps using (2nxe2x88x921) comparison circuits for comparing currents from the (2nxe2x88x921) upper bit reference current cells to the drain current of the memory cell and storing the sensed lower m bits in the data register.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.